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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\code\fpga\test\fpga_project\impl\gwsynthesis\fpga_project.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>D:\code\fpga\test\fpga_project\src\fpga_project.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.02</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Jan  6 21:28:09 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>54</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>53</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">NO.</th>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>1</td>
<td>sys_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>sys_clk_ibuf/I </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>sys_clk</td>
<td>100.000(MHz)</td>
<td>224.194(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sys_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>5.540</td>
<td>count_0_s0/Q</td>
<td>count_13_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.425</td>
</tr>
<tr>
<td>2</td>
<td>5.566</td>
<td>count_0_s0/Q</td>
<td>count_20_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.399</td>
</tr>
<tr>
<td>3</td>
<td>5.724</td>
<td>count_0_s0/Q</td>
<td>count_4_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.241</td>
</tr>
<tr>
<td>4</td>
<td>5.724</td>
<td>count_0_s0/Q</td>
<td>count_18_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.241</td>
</tr>
<tr>
<td>5</td>
<td>5.730</td>
<td>count_0_s0/Q</td>
<td>count_19_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.235</td>
</tr>
<tr>
<td>6</td>
<td>5.776</td>
<td>count_0_s0/Q</td>
<td>count_7_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.189</td>
</tr>
<tr>
<td>7</td>
<td>5.776</td>
<td>count_0_s0/Q</td>
<td>count_10_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.189</td>
</tr>
<tr>
<td>8</td>
<td>5.776</td>
<td>count_0_s0/Q</td>
<td>count_11_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.189</td>
</tr>
<tr>
<td>9</td>
<td>5.788</td>
<td>count_0_s0/Q</td>
<td>count_14_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.177</td>
</tr>
<tr>
<td>10</td>
<td>5.809</td>
<td>count_0_s0/Q</td>
<td>count_0_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.156</td>
</tr>
<tr>
<td>11</td>
<td>5.809</td>
<td>count_0_s0/Q</td>
<td>count_23_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.156</td>
</tr>
<tr>
<td>12</td>
<td>5.902</td>
<td>count_0_s0/Q</td>
<td>count_9_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.063</td>
</tr>
<tr>
<td>13</td>
<td>5.902</td>
<td>count_0_s0/Q</td>
<td>count_12_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.063</td>
</tr>
<tr>
<td>14</td>
<td>5.902</td>
<td>count_0_s0/Q</td>
<td>count_21_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.063</td>
</tr>
<tr>
<td>15</td>
<td>5.902</td>
<td>count_0_s0/Q</td>
<td>count_22_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.063</td>
</tr>
<tr>
<td>16</td>
<td>5.910</td>
<td>count_0_s0/Q</td>
<td>count_8_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.055</td>
</tr>
<tr>
<td>17</td>
<td>5.973</td>
<td>count_0_s0/Q</td>
<td>count_25_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.992</td>
</tr>
<tr>
<td>18</td>
<td>5.973</td>
<td>count_0_s0/Q</td>
<td>count_6_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.992</td>
</tr>
<tr>
<td>19</td>
<td>5.973</td>
<td>count_0_s0/Q</td>
<td>count_15_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.992</td>
</tr>
<tr>
<td>20</td>
<td>6.009</td>
<td>count_0_s0/Q</td>
<td>count_1_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.956</td>
</tr>
<tr>
<td>21</td>
<td>6.009</td>
<td>count_0_s0/Q</td>
<td>count_2_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.956</td>
</tr>
<tr>
<td>22</td>
<td>6.009</td>
<td>count_0_s0/Q</td>
<td>count_3_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.956</td>
</tr>
<tr>
<td>23</td>
<td>6.009</td>
<td>count_0_s0/Q</td>
<td>count_16_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.956</td>
</tr>
<tr>
<td>24</td>
<td>6.045</td>
<td>count_0_s0/Q</td>
<td>count_5_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.920</td>
</tr>
<tr>
<td>25</td>
<td>6.166</td>
<td>count_0_s0/Q</td>
<td>count_24_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.799</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.425</td>
<td>count_2_s0/Q</td>
<td>count_2_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>2</td>
<td>0.425</td>
<td>count_3_s0/Q</td>
<td>count_3_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.436</td>
</tr>
<tr>
<td>3</td>
<td>0.427</td>
<td>count_4_s0/Q</td>
<td>count_4_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.438</td>
</tr>
<tr>
<td>4</td>
<td>0.427</td>
<td>count_6_s0/Q</td>
<td>count_6_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.438</td>
</tr>
<tr>
<td>5</td>
<td>0.427</td>
<td>count_7_s0/Q</td>
<td>count_7_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.438</td>
</tr>
<tr>
<td>6</td>
<td>0.427</td>
<td>count_19_s0/Q</td>
<td>count_19_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.438</td>
</tr>
<tr>
<td>7</td>
<td>0.428</td>
<td>count_13_s0/Q</td>
<td>count_13_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.439</td>
</tr>
<tr>
<td>8</td>
<td>0.428</td>
<td>count_17_s0/Q</td>
<td>count_17_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.439</td>
</tr>
<tr>
<td>9</td>
<td>0.430</td>
<td>count_24_s0/Q</td>
<td>count_24_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.441</td>
</tr>
<tr>
<td>10</td>
<td>0.483</td>
<td>count_1_s0/Q</td>
<td>count_1_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.494</td>
</tr>
<tr>
<td>11</td>
<td>0.483</td>
<td>count_15_s0/Q</td>
<td>count_15_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.494</td>
</tr>
<tr>
<td>12</td>
<td>0.539</td>
<td>count_14_s0/Q</td>
<td>count_14_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.550</td>
</tr>
<tr>
<td>13</td>
<td>0.541</td>
<td>count_16_s0/Q</td>
<td>count_16_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.552</td>
</tr>
<tr>
<td>14</td>
<td>0.557</td>
<td>count_0_s0/Q</td>
<td>count_0_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.568</td>
</tr>
<tr>
<td>15</td>
<td>0.557</td>
<td>count_5_s0/Q</td>
<td>count_5_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.568</td>
</tr>
<tr>
<td>16</td>
<td>0.557</td>
<td>count_9_s0/Q</td>
<td>count_9_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.568</td>
</tr>
<tr>
<td>17</td>
<td>0.557</td>
<td>count_21_s0/Q</td>
<td>count_21_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.568</td>
</tr>
<tr>
<td>18</td>
<td>0.557</td>
<td>count_22_s0/Q</td>
<td>count_22_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.568</td>
</tr>
<tr>
<td>19</td>
<td>0.559</td>
<td>count_25_s0/Q</td>
<td>count_25_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.570</td>
</tr>
<tr>
<td>20</td>
<td>0.559</td>
<td>count_10_s0/Q</td>
<td>count_10_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.570</td>
</tr>
<tr>
<td>21</td>
<td>0.559</td>
<td>count_12_s0/Q</td>
<td>count_12_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.570</td>
</tr>
<tr>
<td>22</td>
<td>0.560</td>
<td>count_8_s0/Q</td>
<td>count_8_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.571</td>
</tr>
<tr>
<td>23</td>
<td>0.560</td>
<td>count_11_s0/Q</td>
<td>count_11_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.571</td>
</tr>
<tr>
<td>24</td>
<td>0.893</td>
<td>count_20_s0/Q</td>
<td>count_20_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.904</td>
</tr>
<tr>
<td>25</td>
<td>1.042</td>
<td>count_23_s0/Q</td>
<td>count_23_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.053</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_24_s0</td>
</tr>
<tr>
<td>2</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_22_s0</td>
</tr>
<tr>
<td>3</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_18_s0</td>
</tr>
<tr>
<td>4</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_10_s0</td>
</tr>
<tr>
<td>5</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_11_s0</td>
</tr>
<tr>
<td>6</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_19_s0</td>
</tr>
<tr>
<td>7</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_12_s0</td>
</tr>
<tr>
<td>8</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_25_s0</td>
</tr>
<tr>
<td>9</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_13_s0</td>
</tr>
<tr>
<td>10</td>
<td>2.315</td>
<td>3.315</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>count_0_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.540</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.785</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>8.215</td>
<td>0.694</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td>n47_s1/I0</td>
</tr>
<tr>
<td>8.785</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td style=" background: #97FFFF;">n47_s1/F</td>
</tr>
<tr>
<td>8.785</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td style=" font-weight:bold;">count_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td>count_13_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C33[0][A]</td>
<td>count_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.159, 48.786%; route: 2.034, 45.971%; tC2Q: 0.232, 5.242%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.566</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.758</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>8.209</td>
<td>0.688</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[0][A]</td>
<td>n40_s1/I0</td>
</tr>
<tr>
<td>8.758</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C31[0][A]</td>
<td style=" background: #97FFFF;">n40_s1/F</td>
</tr>
<tr>
<td>8.758</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[0][A]</td>
<td style=" font-weight:bold;">count_20_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[0][A]</td>
<td>count_20_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C31[0][A]</td>
<td>count_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 48.605%; route: 2.029, 46.120%; tC2Q: 0.232, 5.274%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.724</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.600</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>8.051</td>
<td>0.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td>n56_s1/I0</td>
</tr>
<tr>
<td>8.600</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" background: #97FFFF;">n56_s1/F</td>
</tr>
<tr>
<td>8.600</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" font-weight:bold;">count_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td>count_4_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C24[1][A]</td>
<td>count_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 50.415%; route: 1.871, 44.114%; tC2Q: 0.232, 5.471%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.724</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.600</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>8.051</td>
<td>0.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td>n42_s1/I0</td>
</tr>
<tr>
<td>8.600</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td style=" background: #97FFFF;">n42_s1/F</td>
</tr>
<tr>
<td>8.600</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td style=" font-weight:bold;">count_18_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td>count_18_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C24[2][B]</td>
<td>count_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 50.415%; route: 1.871, 44.114%; tC2Q: 0.232, 5.471%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.730</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.594</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>8.045</td>
<td>0.525</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td>n41_s1/I2</td>
</tr>
<tr>
<td>8.594</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td style=" background: #97FFFF;">n41_s1/F</td>
</tr>
<tr>
<td>8.594</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td style=" font-weight:bold;">count_19_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td>count_19_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C32[1][A]</td>
<td>count_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 50.483%; route: 1.865, 44.038%; tC2Q: 0.232, 5.478%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.776</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.548</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.999</td>
<td>0.478</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C25[1][A]</td>
<td>n53_s1/I2</td>
</tr>
<tr>
<td>8.548</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C25[1][A]</td>
<td style=" background: #97FFFF;">n53_s1/F</td>
</tr>
<tr>
<td>8.548</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][A]</td>
<td style=" font-weight:bold;">count_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][A]</td>
<td>count_7_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C25[1][A]</td>
<td>count_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 51.040%; route: 1.819, 43.421%; tC2Q: 0.232, 5.539%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.776</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.548</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.999</td>
<td>0.478</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C25[0][B]</td>
<td>n50_s1/I0</td>
</tr>
<tr>
<td>8.548</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C25[0][B]</td>
<td style=" background: #97FFFF;">n50_s1/F</td>
</tr>
<tr>
<td>8.548</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[0][B]</td>
<td style=" font-weight:bold;">count_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[0][B]</td>
<td>count_10_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C25[0][B]</td>
<td>count_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 51.040%; route: 1.819, 43.421%; tC2Q: 0.232, 5.539%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.776</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.548</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.999</td>
<td>0.478</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C25[1][B]</td>
<td>n49_s1/I2</td>
</tr>
<tr>
<td>8.548</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C25[1][B]</td>
<td style=" background: #97FFFF;">n49_s1/F</td>
</tr>
<tr>
<td>8.548</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][B]</td>
<td style=" font-weight:bold;">count_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][B]</td>
<td>count_11_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C25[1][B]</td>
<td>count_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 51.040%; route: 1.819, 43.421%; tC2Q: 0.232, 5.539%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.788</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.536</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.445</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[2][B]</td>
<td>n46_s1/I2</td>
</tr>
<tr>
<td>8.536</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C31[2][B]</td>
<td style=" background: #97FFFF;">n46_s1/F</td>
</tr>
<tr>
<td>8.536</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[2][B]</td>
<td style=" font-weight:bold;">count_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[2][B]</td>
<td>count_14_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C31[2][B]</td>
<td>count_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.159, 51.688%; route: 1.786, 42.757%; tC2Q: 0.232, 5.554%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.809</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.515</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.445</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>n60_s2/I1</td>
</tr>
<tr>
<td>8.515</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td style=" background: #97FFFF;">n60_s2/F</td>
</tr>
<tr>
<td>8.515</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 51.444%; route: 1.786, 42.973%; tC2Q: 0.232, 5.582%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.809</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.515</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.445</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[2][A]</td>
<td>n37_s1/I0</td>
</tr>
<tr>
<td>8.515</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C31[2][A]</td>
<td style=" background: #97FFFF;">n37_s1/F</td>
</tr>
<tr>
<td>8.515</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[2][A]</td>
<td style=" font-weight:bold;">count_23_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[2][A]</td>
<td>count_23_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C31[2][A]</td>
<td>count_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 51.444%; route: 1.786, 42.973%; tC2Q: 0.232, 5.582%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.422</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>8.051</td>
<td>0.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td>n51_s1/I2</td>
</tr>
<tr>
<td>8.422</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" background: #97FFFF;">n51_s1/F</td>
</tr>
<tr>
<td>8.422</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" font-weight:bold;">count_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td>count_9_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C24[0][B]</td>
<td>count_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.960, 48.243%; route: 1.871, 46.047%; tC2Q: 0.232, 5.710%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.422</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>8.051</td>
<td>0.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td>n48_s1/I2</td>
</tr>
<tr>
<td>8.422</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" background: #97FFFF;">n48_s1/F</td>
</tr>
<tr>
<td>8.422</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" font-weight:bold;">count_12_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td>count_12_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C24[1][B]</td>
<td>count_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.960, 48.243%; route: 1.871, 46.047%; tC2Q: 0.232, 5.710%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.422</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>8.051</td>
<td>0.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C32[1][B]</td>
<td>n39_s1/I0</td>
</tr>
<tr>
<td>8.422</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C32[1][B]</td>
<td style=" background: #97FFFF;">n39_s1/F</td>
</tr>
<tr>
<td>8.422</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C32[1][B]</td>
<td style=" font-weight:bold;">count_21_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][B]</td>
<td>count_21_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C32[1][B]</td>
<td>count_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.960, 48.243%; route: 1.871, 46.047%; tC2Q: 0.232, 5.710%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.422</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>8.051</td>
<td>0.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td>n38_s1/I2</td>
</tr>
<tr>
<td>8.422</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td style=" background: #97FFFF;">n38_s1/F</td>
</tr>
<tr>
<td>8.422</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td style=" font-weight:bold;">count_22_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td>count_22_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C32[0][B]</td>
<td>count_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.960, 48.243%; route: 1.871, 46.047%; tC2Q: 0.232, 5.710%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.910</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.415</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.953</td>
<td>0.432</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[0][B]</td>
<td>n52_s2/I0</td>
</tr>
<tr>
<td>8.415</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C26[0][B]</td>
<td style=" background: #97FFFF;">n52_s2/F</td>
</tr>
<tr>
<td>8.415</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[0][B]</td>
<td style=" font-weight:bold;">count_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[0][B]</td>
<td>count_8_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C26[0][B]</td>
<td>count_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.051, 50.577%; route: 1.772, 43.702%; tC2Q: 0.232, 5.721%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.973</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.352</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.803</td>
<td>0.282</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[0][B]</td>
<td>n35_s1/I3</td>
</tr>
<tr>
<td>8.352</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C30[0][B]</td>
<td style=" background: #97FFFF;">n35_s1/F</td>
</tr>
<tr>
<td>8.352</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[0][B]</td>
<td style=" font-weight:bold;">count_25_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[0][B]</td>
<td>count_25_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C30[0][B]</td>
<td>count_25_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 53.553%; route: 1.622, 40.636%; tC2Q: 0.232, 5.811%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.973</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.352</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.803</td>
<td>0.282</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[1][A]</td>
<td>n54_s1/I2</td>
</tr>
<tr>
<td>8.352</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C26[1][A]</td>
<td style=" background: #97FFFF;">n54_s1/F</td>
</tr>
<tr>
<td>8.352</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[1][A]</td>
<td style=" font-weight:bold;">count_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[1][A]</td>
<td>count_6_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C26[1][A]</td>
<td>count_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 53.553%; route: 1.622, 40.636%; tC2Q: 0.232, 5.811%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.973</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.352</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.803</td>
<td>0.282</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][A]</td>
<td>n45_s1/I2</td>
</tr>
<tr>
<td>8.352</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C30[2][A]</td>
<td style=" background: #97FFFF;">n45_s1/F</td>
</tr>
<tr>
<td>8.352</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[2][A]</td>
<td style=" font-weight:bold;">count_15_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[2][A]</td>
<td>count_15_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C30[2][A]</td>
<td>count_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.138, 53.553%; route: 1.622, 40.636%; tC2Q: 0.232, 5.811%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.009</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.745</td>
<td>0.224</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[2][A]</td>
<td>n59_s1/I0</td>
</tr>
<tr>
<td>8.315</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C27[2][A]</td>
<td style=" background: #97FFFF;">n59_s1/F</td>
</tr>
<tr>
<td>8.315</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][A]</td>
<td style=" font-weight:bold;">count_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][A]</td>
<td>count_1_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C27[2][A]</td>
<td>count_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.159, 54.580%; route: 1.565, 39.555%; tC2Q: 0.232, 5.865%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.009</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.745</td>
<td>0.224</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td>n58_s2/I0</td>
</tr>
<tr>
<td>8.315</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td style=" background: #97FFFF;">n58_s2/F</td>
</tr>
<tr>
<td>8.315</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td style=" font-weight:bold;">count_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td>count_2_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C27[1][A]</td>
<td>count_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.159, 54.580%; route: 1.565, 39.555%; tC2Q: 0.232, 5.865%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.009</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.745</td>
<td>0.224</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td>n57_s1/I2</td>
</tr>
<tr>
<td>8.315</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td style=" background: #97FFFF;">n57_s1/F</td>
</tr>
<tr>
<td>8.315</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td style=" font-weight:bold;">count_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td>count_3_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C27[0][A]</td>
<td>count_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.159, 54.580%; route: 1.565, 39.555%; tC2Q: 0.232, 5.865%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.009</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.521</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.745</td>
<td>0.224</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[2][B]</td>
<td>n44_s1/I2</td>
</tr>
<tr>
<td>8.315</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C27[2][B]</td>
<td style=" background: #97FFFF;">n44_s1/F</td>
</tr>
<tr>
<td>8.315</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][B]</td>
<td style=" font-weight:bold;">count_16_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][B]</td>
<td>count_16_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C27[2][B]</td>
<td>count_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.159, 54.580%; route: 1.565, 39.555%; tC2Q: 0.232, 5.865%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.045</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.280</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.090</td>
<td>0.440</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td>n35_s5/I1</td>
</tr>
<tr>
<td>6.607</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C26[2][A]</td>
<td style=" background: #97FFFF;">n35_s5/F</td>
</tr>
<tr>
<td>7.004</td>
<td>0.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[2][B]</td>
<td>n35_s3/I0</td>
</tr>
<tr>
<td>7.553</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>25</td>
<td>R18C28[2][B]</td>
<td style=" background: #97FFFF;">n35_s3/F</td>
</tr>
<tr>
<td>7.731</td>
<td>0.178</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][B]</td>
<td>n55_s1/I2</td>
</tr>
<tr>
<td>8.280</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>8.280</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][B]</td>
<td style=" font-weight:bold;">count_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][B]</td>
<td>count_5_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C27[1][B]</td>
<td>count_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.170, 55.353%; route: 1.518, 38.729%; tC2Q: 0.232, 5.918%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.166</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.158</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.324</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>2.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>4.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>4.591</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>5.095</td>
<td>0.503</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[3][A]</td>
<td>n53_s2/I1</td>
</tr>
<tr>
<td>5.650</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R18C27[3][A]</td>
<td style=" background: #97FFFF;">n53_s2/F</td>
</tr>
<tr>
<td>6.073</td>
<td>0.423</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C25[2][B]</td>
<td>n38_s2/I1</td>
</tr>
<tr>
<td>6.628</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>12</td>
<td>R18C25[2][B]</td>
<td style=" background: #97FFFF;">n38_s2/F</td>
</tr>
<tr>
<td>7.316</td>
<td>0.688</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[3][A]</td>
<td>n35_s2/I1</td>
</tr>
<tr>
<td>7.687</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R18C30[3][A]</td>
<td style=" background: #97FFFF;">n35_s2/F</td>
</tr>
<tr>
<td>7.696</td>
<td>0.009</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[1][A]</td>
<td>n36_s1/I2</td>
</tr>
<tr>
<td>8.158</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C30[1][A]</td>
<td style=" background: #97FFFF;">n36_s1/F</td>
</tr>
<tr>
<td>8.158</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[1][A]</td>
<td style=" font-weight:bold;">count_24_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>12.088</td>
<td>2.088</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>14.359</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[1][A]</td>
<td>count_24_s0/CLK</td>
</tr>
<tr>
<td>14.324</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C30[1][A]</td>
<td>count_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.943, 51.150%; route: 1.624, 42.743%; tC2Q: 0.232, 6.107%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 2.088, 47.897%; route: 2.271, 52.103%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td>count_2_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C27[1][A]</td>
<td style=" font-weight:bold;">count_2_s0/Q</td>
</tr>
<tr>
<td>3.108</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td>n58_s2/I1</td>
</tr>
<tr>
<td>3.340</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td style=" background: #97FFFF;">n58_s2/F</td>
</tr>
<tr>
<td>3.340</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td style=" font-weight:bold;">count_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td>count_2_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C27[1][A]</td>
<td>count_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td>count_3_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R18C27[0][A]</td>
<td style=" font-weight:bold;">count_3_s0/Q</td>
</tr>
<tr>
<td>3.108</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td>n57_s1/I3</td>
</tr>
<tr>
<td>3.340</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td style=" background: #97FFFF;">n57_s1/F</td>
</tr>
<tr>
<td>3.340</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td style=" font-weight:bold;">count_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td>count_3_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C27[0][A]</td>
<td>count_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.427</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.341</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td>count_4_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C24[1][A]</td>
<td style=" font-weight:bold;">count_4_s0/Q</td>
</tr>
<tr>
<td>3.109</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td>n56_s1/I1</td>
</tr>
<tr>
<td>3.341</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" background: #97FFFF;">n56_s1/F</td>
</tr>
<tr>
<td>3.341</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" font-weight:bold;">count_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td>count_4_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C24[1][A]</td>
<td>count_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.427</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.341</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[1][A]</td>
<td>count_6_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C26[1][A]</td>
<td style=" font-weight:bold;">count_6_s0/Q</td>
</tr>
<tr>
<td>3.109</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[1][A]</td>
<td>n54_s1/I3</td>
</tr>
<tr>
<td>3.341</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C26[1][A]</td>
<td style=" background: #97FFFF;">n54_s1/F</td>
</tr>
<tr>
<td>3.341</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[1][A]</td>
<td style=" font-weight:bold;">count_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[1][A]</td>
<td>count_6_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C26[1][A]</td>
<td>count_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.427</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.341</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][A]</td>
<td>count_7_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C25[1][A]</td>
<td style=" font-weight:bold;">count_7_s0/Q</td>
</tr>
<tr>
<td>3.109</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][A]</td>
<td>n53_s1/I3</td>
</tr>
<tr>
<td>3.341</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C25[1][A]</td>
<td style=" background: #97FFFF;">n53_s1/F</td>
</tr>
<tr>
<td>3.341</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C25[1][A]</td>
<td style=" font-weight:bold;">count_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][A]</td>
<td>count_7_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C25[1][A]</td>
<td>count_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.427</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.341</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_19_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td>count_19_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C32[1][A]</td>
<td style=" font-weight:bold;">count_19_s0/Q</td>
</tr>
<tr>
<td>3.109</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td>n41_s1/I3</td>
</tr>
<tr>
<td>3.341</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td style=" background: #97FFFF;">n41_s1/F</td>
</tr>
<tr>
<td>3.341</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td style=" font-weight:bold;">count_19_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][A]</td>
<td>count_19_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C32[1][A]</td>
<td>count_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.428</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.342</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td>count_13_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C33[0][A]</td>
<td style=" font-weight:bold;">count_13_s0/Q</td>
</tr>
<tr>
<td>3.110</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td>n47_s1/I1</td>
</tr>
<tr>
<td>3.342</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td style=" background: #97FFFF;">n47_s1/F</td>
</tr>
<tr>
<td>3.342</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td style=" font-weight:bold;">count_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C33[0][A]</td>
<td>count_13_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C33[0][A]</td>
<td>count_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.428</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.342</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C28[1][A]</td>
<td>count_17_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C28[1][A]</td>
<td style=" font-weight:bold;">count_17_s0/Q</td>
</tr>
<tr>
<td>3.110</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C28[1][A]</td>
<td>n43_s1/I3</td>
</tr>
<tr>
<td>3.342</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C28[1][A]</td>
<td style=" background: #97FFFF;">n43_s1/F</td>
</tr>
<tr>
<td>3.342</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C28[1][A]</td>
<td style=" font-weight:bold;">count_17_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C28[1][A]</td>
<td>count_17_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C28[1][A]</td>
<td>count_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.430</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_24_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[1][A]</td>
<td>count_24_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R18C30[1][A]</td>
<td style=" font-weight:bold;">count_24_s0/Q</td>
</tr>
<tr>
<td>3.113</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[1][A]</td>
<td>n36_s1/I1</td>
</tr>
<tr>
<td>3.345</td>
<td>0.232</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C30[1][A]</td>
<td style=" background: #97FFFF;">n36_s1/F</td>
</tr>
<tr>
<td>3.345</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[1][A]</td>
<td style=" font-weight:bold;">count_24_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[1][A]</td>
<td>count_24_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C30[1][A]</td>
<td>count_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.232, 52.568%; route: 0.007, 1.662%; tC2Q: 0.202, 45.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.483</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.398</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][A]</td>
<td>count_1_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C27[2][A]</td>
<td style=" font-weight:bold;">count_1_s0/Q</td>
</tr>
<tr>
<td>3.108</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][A]</td>
<td>n59_s1/I1</td>
</tr>
<tr>
<td>3.398</td>
<td>0.290</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C27[2][A]</td>
<td style=" background: #97FFFF;">n59_s1/F</td>
</tr>
<tr>
<td>3.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[2][A]</td>
<td style=" font-weight:bold;">count_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][A]</td>
<td>count_1_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C27[2][A]</td>
<td>count_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.290, 58.652%; route: 0.002, 0.494%; tC2Q: 0.202, 40.854%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.483</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.398</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_15_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[2][A]</td>
<td>count_15_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C30[2][A]</td>
<td style=" font-weight:bold;">count_15_s0/Q</td>
</tr>
<tr>
<td>3.108</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[2][A]</td>
<td>n45_s1/I3</td>
</tr>
<tr>
<td>3.398</td>
<td>0.290</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C30[2][A]</td>
<td style=" background: #97FFFF;">n45_s1/F</td>
</tr>
<tr>
<td>3.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][A]</td>
<td style=" font-weight:bold;">count_15_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[2][A]</td>
<td>count_15_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C30[2][A]</td>
<td>count_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.290, 58.652%; route: 0.002, 0.494%; tC2Q: 0.202, 40.854%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.539</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.453</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_14_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[2][B]</td>
<td>count_14_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C31[2][B]</td>
<td style=" font-weight:bold;">count_14_s0/Q</td>
</tr>
<tr>
<td>3.109</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[2][B]</td>
<td>n46_s1/I3</td>
</tr>
<tr>
<td>3.453</td>
<td>0.344</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C31[2][B]</td>
<td style=" background: #97FFFF;">n46_s1/F</td>
</tr>
<tr>
<td>3.453</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[2][B]</td>
<td style=" font-weight:bold;">count_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[2][B]</td>
<td>count_14_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C31[2][B]</td>
<td>count_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.344, 62.583%; route: 0.004, 0.667%; tC2Q: 0.202, 36.750%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.541</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.455</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_16_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][B]</td>
<td>count_16_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C27[2][B]</td>
<td style=" font-weight:bold;">count_16_s0/Q</td>
</tr>
<tr>
<td>3.111</td>
<td>0.006</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][B]</td>
<td>n44_s1/I3</td>
</tr>
<tr>
<td>3.455</td>
<td>0.344</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C27[2][B]</td>
<td style=" background: #97FFFF;">n44_s1/F</td>
</tr>
<tr>
<td>3.455</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[2][B]</td>
<td style=" font-weight:bold;">count_16_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[2][B]</td>
<td>count_16_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C27[2][B]</td>
<td>count_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.344, 62.306%; route: 0.006, 1.107%; tC2Q: 0.202, 36.587%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.557</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/Q</td>
</tr>
<tr>
<td>3.108</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>n60_s2/I0</td>
</tr>
<tr>
<td>3.472</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td style=" background: #97FFFF;">n60_s2/F</td>
</tr>
<tr>
<td>3.472</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td style=" font-weight:bold;">count_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>count_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.557</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][B]</td>
<td>count_5_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C27[1][B]</td>
<td style=" font-weight:bold;">count_5_s0/Q</td>
</tr>
<tr>
<td>3.108</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][B]</td>
<td>n55_s1/I3</td>
</tr>
<tr>
<td>3.472</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C27[1][B]</td>
<td style=" background: #97FFFF;">n55_s1/F</td>
</tr>
<tr>
<td>3.472</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C27[1][B]</td>
<td style=" font-weight:bold;">count_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][B]</td>
<td>count_5_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C27[1][B]</td>
<td>count_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.557</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td>count_9_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C24[0][B]</td>
<td style=" font-weight:bold;">count_9_s0/Q</td>
</tr>
<tr>
<td>3.108</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td>n51_s1/I3</td>
</tr>
<tr>
<td>3.472</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" background: #97FFFF;">n51_s1/F</td>
</tr>
<tr>
<td>3.472</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" font-weight:bold;">count_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td>count_9_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C24[0][B]</td>
<td>count_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.557</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][B]</td>
<td>count_21_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C32[1][B]</td>
<td style=" font-weight:bold;">count_21_s0/Q</td>
</tr>
<tr>
<td>3.108</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][B]</td>
<td>n39_s1/I1</td>
</tr>
<tr>
<td>3.472</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C32[1][B]</td>
<td style=" background: #97FFFF;">n39_s1/F</td>
</tr>
<tr>
<td>3.472</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C32[1][B]</td>
<td style=" font-weight:bold;">count_21_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[1][B]</td>
<td>count_21_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C32[1][B]</td>
<td>count_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.557</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_22_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td>count_22_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R18C32[0][B]</td>
<td style=" font-weight:bold;">count_22_s0/Q</td>
</tr>
<tr>
<td>3.108</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td>n38_s1/I3</td>
</tr>
<tr>
<td>3.472</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td style=" background: #97FFFF;">n38_s1/F</td>
</tr>
<tr>
<td>3.472</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td style=" font-weight:bold;">count_22_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C32[0][B]</td>
<td>count_22_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C32[0][B]</td>
<td>count_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.473</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_25_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[0][B]</td>
<td>count_25_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C30[0][B]</td>
<td style=" font-weight:bold;">count_25_s0/Q</td>
</tr>
<tr>
<td>3.109</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[0][B]</td>
<td>n35_s1/I2</td>
</tr>
<tr>
<td>3.473</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C30[0][B]</td>
<td style=" background: #97FFFF;">n35_s1/F</td>
</tr>
<tr>
<td>3.473</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[0][B]</td>
<td style=" font-weight:bold;">count_25_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C30[0][B]</td>
<td>count_25_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C30[0][B]</td>
<td>count_25_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.473</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[0][B]</td>
<td>count_10_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C25[0][B]</td>
<td style=" font-weight:bold;">count_10_s0/Q</td>
</tr>
<tr>
<td>3.109</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[0][B]</td>
<td>n50_s1/I1</td>
</tr>
<tr>
<td>3.473</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C25[0][B]</td>
<td style=" background: #97FFFF;">n50_s1/F</td>
</tr>
<tr>
<td>3.473</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C25[0][B]</td>
<td style=" font-weight:bold;">count_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[0][B]</td>
<td>count_10_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C25[0][B]</td>
<td>count_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.473</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_12_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td>count_12_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C24[1][B]</td>
<td style=" font-weight:bold;">count_12_s0/Q</td>
</tr>
<tr>
<td>3.109</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td>n48_s1/I3</td>
</tr>
<tr>
<td>3.473</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" background: #97FFFF;">n48_s1/F</td>
</tr>
<tr>
<td>3.473</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" font-weight:bold;">count_12_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td>count_12_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C24[1][B]</td>
<td>count_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.560</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[0][B]</td>
<td>count_8_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C26[0][B]</td>
<td style=" font-weight:bold;">count_8_s0/Q</td>
</tr>
<tr>
<td>3.110</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[0][B]</td>
<td>n52_s2/I1</td>
</tr>
<tr>
<td>3.474</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C26[0][B]</td>
<td style=" background: #97FFFF;">n52_s2/F</td>
</tr>
<tr>
<td>3.474</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C26[0][B]</td>
<td style=" font-weight:bold;">count_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C26[0][B]</td>
<td>count_8_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C26[0][B]</td>
<td>count_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 63.760%; route: 0.005, 0.856%; tC2Q: 0.202, 35.383%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.560</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.474</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][B]</td>
<td>count_11_s0/CLK</td>
</tr>
<tr>
<td>3.105</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C25[1][B]</td>
<td style=" font-weight:bold;">count_11_s0/Q</td>
</tr>
<tr>
<td>3.110</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][B]</td>
<td>n49_s1/I3</td>
</tr>
<tr>
<td>3.474</td>
<td>0.364</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C25[1][B]</td>
<td style=" background: #97FFFF;">n49_s1/F</td>
</tr>
<tr>
<td>3.474</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C25[1][B]</td>
<td style=" font-weight:bold;">count_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C25[1][B]</td>
<td>count_11_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C25[1][B]</td>
<td>count_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.364, 63.760%; route: 0.005, 0.856%; tC2Q: 0.202, 35.383%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.893</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.807</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[0][A]</td>
<td>count_20_s0/CLK</td>
</tr>
<tr>
<td>3.104</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R18C31[0][A]</td>
<td style=" font-weight:bold;">count_20_s0/Q</td>
</tr>
<tr>
<td>3.228</td>
<td>0.124</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[1][A]</td>
<td>n40_s2/I3</td>
</tr>
<tr>
<td>3.572</td>
<td>0.344</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C31[1][A]</td>
<td style=" background: #97FFFF;">n40_s2/F</td>
</tr>
<tr>
<td>3.575</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[0][A]</td>
<td>n40_s1/I1</td>
</tr>
<tr>
<td>3.807</td>
<td>0.232</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C31[0][A]</td>
<td style=" background: #97FFFF;">n40_s1/F</td>
</tr>
<tr>
<td>3.807</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[0][A]</td>
<td style=" font-weight:bold;">count_20_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[0][A]</td>
<td>count_20_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C31[0][A]</td>
<td>count_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.576, 63.714%; route: 0.127, 14.052%; tC2Q: 0.201, 22.234%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.042</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.956</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.914</td>
</tr>
<tr>
<td class="label">From</td>
<td>count_23_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>count_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[2][A]</td>
<td>count_23_s0/CLK</td>
</tr>
<tr>
<td>3.104</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R18C31[2][A]</td>
<td style=" font-weight:bold;">count_23_s0/Q</td>
</tr>
<tr>
<td>3.225</td>
<td>0.120</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[0][B]</td>
<td>n37_s2/I3</td>
</tr>
<tr>
<td>3.589</td>
<td>0.364</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C31[0][B]</td>
<td style=" background: #97FFFF;">n37_s2/F</td>
</tr>
<tr>
<td>3.592</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[2][A]</td>
<td>n37_s1/I1</td>
</tr>
<tr>
<td>3.956</td>
<td>0.364</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C31[2][A]</td>
<td style=" background: #97FFFF;">n37_s1/F</td>
</tr>
<tr>
<td>3.956</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[2][A]</td>
<td style=" font-weight:bold;">count_23_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>1.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOR29[A]</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>2.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C31[2][A]</td>
<td>count_23_s0/CLK</td>
</tr>
<tr>
<td>2.914</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C31[2][A]</td>
<td>count_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.728, 69.152%; route: 0.124, 11.756%; tC2Q: 0.201, 19.093%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.392, 47.946%; route: 1.511, 52.054%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_24_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_24_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_24_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_22_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_22_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_22_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_18_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_18_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_18_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_10_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_10_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_10_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_11_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_11_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_11_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_19_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_19_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_19_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_12_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_12_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_12_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_25_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_25_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_25_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_13_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_13_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_13_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.315</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>count_0_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>7.314</td>
<td>2.314</td>
<td>tINS</td>
<td>FF</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>9.588</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>count_0_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>sys_clk_ibuf/I</td>
</tr>
<tr>
<td>11.392</td>
<td>1.392</td>
<td>tINS</td>
<td>RR</td>
<td>sys_clk_ibuf/O</td>
</tr>
<tr>
<td>12.903</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>count_0_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>26</td>
<td>sys_clk_d</td>
<td>5.540</td>
<td>2.274</td>
</tr>
<tr>
<td>25</td>
<td>n35_7</td>
<td>5.540</td>
<td>0.694</td>
</tr>
<tr>
<td>12</td>
<td>n38_6</td>
<td>5.858</td>
<td>0.688</td>
</tr>
<tr>
<td>9</td>
<td>n53_6</td>
<td>5.540</td>
<td>0.440</td>
</tr>
<tr>
<td>6</td>
<td>count[24]</td>
<td>6.665</td>
<td>0.412</td>
</tr>
<tr>
<td>6</td>
<td>n41_6</td>
<td>6.298</td>
<td>0.437</td>
</tr>
<tr>
<td>5</td>
<td>count[16]</td>
<td>6.451</td>
<td>0.259</td>
</tr>
<tr>
<td>5</td>
<td>count[19]</td>
<td>5.989</td>
<td>0.176</td>
</tr>
<tr>
<td>5</td>
<td>count[17]</td>
<td>7.287</td>
<td>0.188</td>
</tr>
<tr>
<td>5</td>
<td>count[13]</td>
<td>6.298</td>
<td>0.670</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R18C27</td>
<td>69.44%</td>
</tr>
<tr>
<td>R18C31</td>
<td>58.33%</td>
</tr>
<tr>
<td>R18C30</td>
<td>55.56%</td>
</tr>
<tr>
<td>R18C25</td>
<td>50.00%</td>
</tr>
<tr>
<td>R18C24</td>
<td>47.22%</td>
</tr>
<tr>
<td>R18C26</td>
<td>45.83%</td>
</tr>
<tr>
<td>R18C32</td>
<td>38.89%</td>
</tr>
<tr>
<td>R18C28</td>
<td>36.11%</td>
</tr>
<tr>
<td>R18C33</td>
<td>29.17%</td>
</tr>
<tr>
<td>R18C29</td>
<td>13.89%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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